High Performance Multipliers Using Hybrid Adder

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Sumit Raj, Utkarsh Chaurasia, Aayush Bahukhandi, Poornima Mittal

Résumé

Multiplier is a key component in most of the digital signal processing applications. With the development in the field of VLSI, designers are greatly concerned about achieving low power consumption and high speed. As the multiplier block requires a significant amount of power and plays a significant role in the circuit's speed, optimising it would enhance the circuit's performance. In this paper, a hybrid adder using a combination of transmission gate and pass transistor logic is proposed. Different multipliers are implemented using the proposed hybrid adder. Multiplier with proposed hybrid adder is compared with the multipliers using existing full adder architecture. Performance analysis is done based on different parameters such as delay, power and power-delay product. Power-delay product in multipliers with proposed adder is significantly reduced as compared to multipliers based on mirror and transmission gate adders, implying that the proposed design shows better performance. And in the proposed design, Wallace Tree multiplier and Vedic multiplier show best performance as they have lowest power-delay product, which is approximately half as compared to Bit Array and Baugh Wooley multiplier. All the circuits are designed and simulated using 90nm technology library in the Cadence Virtuoso tool.

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